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An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI.

, , , and . ESSCIRC, page 437-440. IEEE, (2016)

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A 16Kb 10T-SRAM with 4x read-power reduction., and . ISCAS, page 3485-3488. IEEE, (2010)NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells., , , and . ISOCC, page 200-203. IEEE, (2012)A new match line sensing technique in Content Addressable Memory., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2011)An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI., , , and . IEEE J. Solid State Circuits, 54 (7): 2091-2101 (2019)A low-power CAM with efficient power and delay trade-off., , , and . ISCAS, page 2573-2576. IEEE, (2011)The Initialization Factor: Understanding its Impact on Active Learning for Analog Circuit Design., , , , , , , and . ISCAS, page 1-5. IEEE, (2024)Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement., and . ISOCC, page 163-166. IEEE, (2011)Leakage-resilient memory-based physical unclonable function using phase change material., , , , and . ICCST, page 1-6. IEEE, (2014)Body-bootstrapped-buffer circuit for CMOS static power reduction., , , , and . APCCAS, page 842-845. IEEE, (2008)Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes., , , and . ISCAS, page 1410-1413. IEEE, (2015)