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Disambiguation of "Daveau, Jean-Marc"

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28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.

, , , , , , , , and . ESSCIRC, page 108-111. IEEE, (2015)

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Jean-Marc Régis

Jean-Marc Schaller

Jean-Marc Chanton

Jean-Marc Leutenegger

Jean-Marc Gauer

 

Other publications of authors with the same name

Automating the Design of SOCs Using Cores., , , , , , , and . IEEE Des. Test Comput., 18 (5): 32-45 (2001)FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip., , , , , , , and . DFT, page 1-6. IEEE, (2021)Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation., , , and . ICECS, page 263-267. IEEE, (2010)A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI., , , , , and . IEEE J. Solid State Circuits, 53 (7): 2088-2100 (2018)28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors., , , , , , , , and . ESSCIRC, page 108-111. IEEE, (2015)30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation., , , , , , , and . ESSCIRC, page 37-40. IEEE, (2016)Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS., , , , , and . IOLTS, page 46-48. IEEE Computer Society, (2008)Formal Temporal Characterization of Register Vulnerability in Digital Circuits., , , and . ISVLSI, page 1-6. IEEE, (2023)Communication Interface Synthesis for Multilanguage Specifications., , , , , and . IEEE International Workshop on Rapid System Prototyping, page 15-20. IEEE Computer Society, (1999)Synthesis of system-level communication by an allocation-based approach., , and . ISSS, page 150-155. ACM, (1995)