%0 Journal Article %1 journals/corr/abs-1911-04378 %A Grycel, Jacob T. %A Walls, Robert J. %D 2019 %J CoRR %K dblp %T DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs. %U http://dblp.uni-trier.de/db/journals/corr/corr1911.html#abs-1911-04378 %V abs/1911.04378

@article{journals/corr/abs-1911-04378, added-at = {2019-12-01T00:00:00.000+0100}, author = {Grycel, Jacob T. and Walls, Robert J.}, biburl = {https://www.bibsonomy.org/bibtex/2f1471b0a0d670a0714e9c32a7c3b9e4e/dblp}, ee = {http://arxiv.org/abs/1911.04378}, interhash = {089dac6d51b4db2ac8c85c54f0ae983d}, intrahash = {f1471b0a0d670a0714e9c32a7c3b9e4e}, journal = {CoRR}, keywords = {dblp}, timestamp = {2019-12-03T11:39:05.000+0100}, title = {DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs.}, url = {http://dblp.uni-trier.de/db/journals/corr/corr1911.html#abs-1911-04378}, volume = {abs/1911.04378}, year = 2019 }