%0 Journal Article %1 journals/mam/ResanoVMVC04 %A Resano, Javier %A Verkest, Diederik %A Mozos, Daniel %A Vernalde, Serge %A Catthoor, Francky %D 2004 %J Microprocess. Microsystems %K dblp %N 5-6 %P 291-301 %T A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. %U http://dblp.uni-trier.de/db/journals/mam/mam28.html#ResanoVMVC04 %V 28

@article{journals/mam/ResanoVMVC04, added-at = {2020-05-18T00:00:00.000+0200}, author = {Resano, Javier and Verkest, Diederik and Mozos, Daniel and Vernalde, Serge and Catthoor, Francky}, biburl = {https://www.bibsonomy.org/bibtex/2fbfe65e8444fef38724cb122167843b8/dblp}, ee = {https://www.wikidata.org/entity/Q61688135}, interhash = {093705760220d77043d2330a4f0437f4}, intrahash = {fbfe65e8444fef38724cb122167843b8}, journal = {Microprocess. Microsystems}, keywords = {dblp}, number = {5-6}, pages = {291-301}, timestamp = {2020-05-19T11:56:03.000+0200}, title = {A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.}, url = {http://dblp.uni-trier.de/db/journals/mam/mam28.html#ResanoVMVC04}, volume = 28, year = 2004 }