%0 Journal Article %1 journals/jssc/JiaWJG20 %A Jia, Tianyu %A Wei, Yijie %A Joseph, Russ %A Gu, Jie %D 2020 %J IEEE J. Solid State Circuits %K dblp %N 8 %P 2259-2269 %T An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. %U http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#JiaWJG20 %V 55

@article{journals/jssc/JiaWJG20, added-at = {2021-03-02T00:00:00.000+0100}, author = {Jia, Tianyu and Wei, Yijie and Joseph, Russ and Gu, Jie}, biburl = {https://www.bibsonomy.org/bibtex/2edd860d743878214f68e751ed44afaf0/dblp}, ee = {https://doi.org/10.1109/JSSC.2020.2979451}, interhash = {02592e5d2032f19461890d4d6fae4cbe}, intrahash = {edd860d743878214f68e751ed44afaf0}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 8, pages = {2259-2269}, timestamp = {2024-04-08T10:43:37.000+0200}, title = {An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#JiaWJG20}, volume = 55, year = 2020 }