%0 Conference Paper %1 conf/date/CiricYS00 %A Ciric, Jovanka %A Yee, Gin %A Sechen, Carl %B DATE %D 2000 %E Bolsens, Ivo %I IEEE Computer Society / ACM %K dblp %P 277-282 %T Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. %U http://dblp.uni-trier.de/db/conf/date/date2000.html#CiricYS00 %@ 0-7695-0537-6

@inproceedings{conf/date/CiricYS00, added-at = {2023-03-24T00:00:00.000+0100}, author = {Ciric, Jovanka and Yee, Gin and Sechen, Carl}, biburl = {https://www.bibsonomy.org/bibtex/2815d3fa00de39c0d3ccfb6c7e6af414c/dblp}, booktitle = {DATE}, crossref = {conf/date/2000}, editor = {Bolsens, Ivo}, ee = {https://doi.org/10.1145/343647.343781}, interhash = {08150577af0fb17bd9ba8adc523cb659}, intrahash = {815d3fa00de39c0d3ccfb6c7e6af414c}, isbn = {0-7695-0537-6}, keywords = {dblp}, pages = {277-282}, publisher = {IEEE Computer Society / ACM}, timestamp = {2024-04-10T06:52:58.000+0200}, title = {Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic.}, url = {http://dblp.uni-trier.de/db/conf/date/date2000.html#CiricYS00}, year = 2000 }