%0 Journal Article %1 journals/jssc/FujisawaNTKMNUD05 %A Fujisawa, Hiroki %A Nakamura, Masayuki %A Takai, Yasuhiro %A Koshikawa, Yasuji %A Matano, Tatsuya %A Narui, Seiji %A Usuki, Narikazu %A Dono, Chiaki %A Miyatake, Shinichi %A Morino, Makoto %A Arai, Koji %A Kubouchi, Shuichi %A Fujii, Isamu %A Yoko, Hideyuki %A Adachi, Takao %D 2005 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 862-869 %T 1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. %U http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#FujisawaNTKMNUD05 %V 40

@article{journals/jssc/FujisawaNTKMNUD05, added-at = {2022-03-02T00:00:00.000+0100}, author = {Fujisawa, Hiroki and Nakamura, Masayuki and Takai, Yasuhiro and Koshikawa, Yasuji and Matano, Tatsuya and Narui, Seiji and Usuki, Narikazu and Dono, Chiaki and Miyatake, Shinichi and Morino, Makoto and Arai, Koji and Kubouchi, Shuichi and Fujii, Isamu and Yoko, Hideyuki and Adachi, Takao}, biburl = {https://www.bibsonomy.org/bibtex/2f1b2e5c04c74f1cacb01b0c3359b3c79/dblp}, ee = {https://doi.org/10.1109/JSSC.2005.845555}, interhash = {0d3f5706295b491dfbb47d0dfe800232}, intrahash = {f1b2e5c04c74f1cacb01b0c3359b3c79}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {862-869}, timestamp = {2024-04-08T10:44:28.000+0200}, title = {1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#FujisawaNTKMNUD05}, volume = 40, year = 2005 }