%0 Journal Article %1 journals/jssc/VarzaghaniY06a %A Varzaghani, Aida %A Yang, Chih-Kong Ken %D 2006 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 935-944 %T A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. %U http://dblp.uni-trier.de/db/journals/jssc/jssc41.html#VarzaghaniY06a %V 41

@article{journals/jssc/VarzaghaniY06a, added-at = {2021-10-15T00:00:00.000+0200}, author = {Varzaghani, Aida and Yang, Chih-Kong Ken}, biburl = {https://www.bibsonomy.org/bibtex/2554286be7be442e46c89396d74a695d3/dblp}, ee = {https://doi.org/10.1109/JSSC.2006.870911}, interhash = {0f6d61f432820a16689c6dc147d118bd}, intrahash = {554286be7be442e46c89396d74a695d3}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {935-944}, timestamp = {2024-04-08T10:42:52.000+0200}, title = {A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc41.html#VarzaghaniY06a}, volume = 41, year = 2006 }