%0 Journal Article %1 journals/fmsd/BerezinCBZ02 %A Berezin, Sergey %A Clarke, Edmund M. %A Biere, Armin %A Zhu, Yunshan %D 2002 %J Formal Methods Syst. Des. %K dblp %N 2 %P 159-186 %T Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function. %U http://dblp.uni-trier.de/db/journals/fmsd/fmsd20.html#BerezinCBZ02 %V 20

@article{journals/fmsd/BerezinCBZ02, added-at = {2020-03-13T00:00:00.000+0100}, author = {Berezin, Sergey and Clarke, Edmund M. and Biere, Armin and Zhu, Yunshan}, biburl = {https://www.bibsonomy.org/bibtex/2326572bce126fdcfb259cd7f45a96d80/dblp}, ee = {https://doi.org/10.1023/A:1014170513439}, interhash = {109ce9125f2a17fe940ef12995a4f169}, intrahash = {326572bce126fdcfb259cd7f45a96d80}, journal = {Formal Methods Syst. Des.}, keywords = {dblp}, number = 2, pages = {159-186}, timestamp = {2020-03-14T11:51:48.000+0100}, title = {Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function.}, url = {http://dblp.uni-trier.de/db/journals/fmsd/fmsd20.html#BerezinCBZ02}, volume = 20, year = 2002 }