%0 Journal Article %1 journals/jssc/WangABCCHHJKKLN08 %A Wang, Yih %A Ahn, Hong Jo %A Bhattacharya, Uddalak %A Chen, Zhanping %A Coan, Tom %A Hamzaoglu, Fatih %A Hafez, Walid M. %A Jan, Chia-Hong %A Kolar, Pramod %A Kulkarni, Sarvesh H. %A Lin, Jie-Feng %A Ng, Yong-Gee %A Post, Ian %A Wei, Liqiong %A Zhang, Ying %A Zhang, Kevin %A Bohr, Mark %D 2008 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 172-179 %T A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. %U http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#WangABCCHHJKKLN08 %V 43

@article{journals/jssc/WangABCCHHJKKLN08, added-at = {2021-10-14T00:00:00.000+0200}, author = {Wang, Yih and Ahn, Hong Jo and Bhattacharya, Uddalak and Chen, Zhanping and Coan, Tom and Hamzaoglu, Fatih and Hafez, Walid M. and Jan, Chia-Hong and Kolar, Pramod and Kulkarni, Sarvesh H. and Lin, Jie-Feng and Ng, Yong-Gee and Post, Ian and Wei, Liqiong and Zhang, Ying and Zhang, Kevin and Bohr, Mark}, biburl = {https://www.bibsonomy.org/bibtex/21a157087a3d4cd93ad4e59eaf4b6795e/dblp}, ee = {https://doi.org/10.1109/JSSC.2007.907996}, interhash = {112ef00ad6560c268ce2f8a8bbebed5e}, intrahash = {1a157087a3d4cd93ad4e59eaf4b6795e}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {172-179}, timestamp = {2024-04-08T10:44:32.000+0200}, title = {A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#WangABCCHHJKKLN08}, volume = 43, year = 2008 }