%0 Journal Article %1 journals/tecs/0006FPJ14 %A Yang, Qiang %A Fu, Jian %A Poss, Raphael %A Jesshope, Chris R. %D 2014 %J ACM Trans. Embed. Comput. Syst. %K dblp %N 3s %P 103:1-103:21 %T On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. %U http://dblp.uni-trier.de/db/journals/tecs/tecs13.html#0006FPJ14 %V 13

@article{journals/tecs/0006FPJ14, added-at = {2020-09-08T00:00:00.000+0200}, author = {Yang, Qiang and Fu, Jian and Poss, Raphael and Jesshope, Chris R.}, biburl = {https://www.bibsonomy.org/bibtex/2d473ce61df8237e362b1c20b33be8281/dblp}, ee = {https://doi.org/10.1145/2567931}, interhash = {11de5e74a8d38b1d6593ed372799a963}, intrahash = {d473ce61df8237e362b1c20b33be8281}, journal = {ACM Trans. Embed. Comput. Syst.}, keywords = {dblp}, number = {3s}, pages = {103:1-103:21}, timestamp = {2020-09-09T12:40:28.000+0200}, title = {On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches.}, url = {http://dblp.uni-trier.de/db/journals/tecs/tecs13.html#0006FPJ14}, volume = 13, year = 2014 }