Inproceedings,
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.
J. Chang, Y. Chen, G. Chan, K. Lin, P. Wang, Y. Lin, S. Chen, P. Lin, C. Wu, C. Lin, Y. Nien, H. Fujiwara, A. Katoch, R. Lee, H. Liao, J. Liaw, S. Wu, and Q. Li.VLSI Technology and Circuits, page 1-2. IEEE, (2023)
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- conf/vlsit/ChangCCLWLCLWLN23
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- inproceedings
- booktitle
- VLSI Technology and Circuits
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- 2023
- pages
- 1-2
- publisher
- IEEE
- crossref
- conf/vlsit/2023
- ee
- https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185287
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- 978-4-86348-806-9
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- http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#ChangCCLWLCLWLN23
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%1 conf/vlsit/ChangCCLWLCLWLN23
%A Chang, Jonathan
%A Chen, Yen-Huei
%A Chan, Gary
%A Lin, Kuo-Cheng
%A Wang, Po-Sheng
%A Lin, Yangsyu
%A Chen, Sevic
%A Lin, Peijiun
%A Wu, Ching-Wei
%A Lin, Chih-Yu
%A Nien, Yi-Hsin
%A Fujiwara, Hidehiro
%A Katoch, Atul
%A Lee, Robin
%A Liao, Hung-Jen
%A Liaw, Jhon-Jhy
%A Wu, Shien-Yang Michael
%A Li, Quincy
%B VLSI Technology and Circuits
%D 2023
%I IEEE
%K dblp
%P 1-2
%T A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.
%U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#ChangCCLWLCLWLN23
%@ 978-4-86348-806-9
@inproceedings{conf/vlsit/ChangCCLWLCLWLN23,
added-at = {2023-07-28T00:00:00.000+0200},
author = {Chang, Jonathan and Chen, Yen-Huei and Chan, Gary and Lin, Kuo-Cheng and Wang, Po-Sheng and Lin, Yangsyu and Chen, Sevic and Lin, Peijiun and Wu, Ching-Wei and Lin, Chih-Yu and Nien, Yi-Hsin and Fujiwara, Hidehiro and Katoch, Atul and Lee, Robin and Liao, Hung-Jen and Liaw, Jhon-Jhy and Wu, Shien-Yang Michael and Li, Quincy},
biburl = {https://www.bibsonomy.org/bibtex/2ecfe25758572d24a9d93422901a733c7/dblp},
booktitle = {VLSI Technology and Circuits},
crossref = {conf/vlsit/2023},
ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185287},
interhash = {184785390cf66dfeb4405a98fd35feba},
intrahash = {ecfe25758572d24a9d93422901a733c7},
isbn = {978-4-86348-806-9},
keywords = {dblp},
pages = {1-2},
publisher = {IEEE},
timestamp = {2024-04-09T19:13:01.000+0200},
title = {A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.},
url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#ChangCCLWLCLWLN23},
year = 2023
}