%0 Journal Article %1 journals/jcsc/SavicSNPJ14 %A Savic, Nemanja %A Stojcev, Mile K. %A Nikolic, Tatjana R. %A Petrovic, Vladimir %A Jovanovic, Goran S. %D 2014 %J Journal of Circuits, Systems, and Computers %K dblp %N 1 %T Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation. %U http://dblp.uni-trier.de/db/journals/jcsc/jcsc23.html#SavicSNPJ14 %V 23

@article{journals/jcsc/SavicSNPJ14, added-at = {2016-03-31T00:00:00.000+0200}, author = {Savic, Nemanja and Stojcev, Mile K. and Nikolic, Tatjana R. and Petrovic, Vladimir and Jovanovic, Goran S.}, biburl = {https://www.bibsonomy.org/bibtex/2d4e503452de28b78fc186e9f5c11f009/dblp}, ee = {http://dx.doi.org/10.1142/S0218126614500029}, interhash = {1aae241063af14ab1eddc377260e1a4a}, intrahash = {d4e503452de28b78fc186e9f5c11f009}, journal = {Journal of Circuits, Systems, and Computers}, keywords = {dblp}, number = 1, timestamp = {2016-04-01T11:35:43.000+0200}, title = {Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation.}, url = {http://dblp.uni-trier.de/db/journals/jcsc/jcsc23.html#SavicSNPJ14}, volume = 23, year = 2014 }