%0 Journal Article %1 journals/tvlsi/ChangGZ05 %A Chang, Chip-Hong %A Gu, Jiangmin %A Zhang, Mingyan %D 2005 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 6 %P 686-695 %T A review of 0.18-μm full adder performances for tree structured arithmetic circuits. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#ChangGZ05 %V 13

@article{journals/tvlsi/ChangGZ05, added-at = {2021-07-27T00:00:00.000+0200}, author = {Chang, Chip-Hong and Gu, Jiangmin and Zhang, Mingyan}, biburl = {https://www.bibsonomy.org/bibtex/2eda0857678523ad4125cbd83a0dcebc2/dblp}, ee = {https://www.wikidata.org/entity/Q57265228}, interhash = {1b7826860d890c9098b2f2901457a981}, intrahash = {eda0857678523ad4125cbd83a0dcebc2}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 6, pages = {686-695}, timestamp = {2024-04-08T14:33:21.000+0200}, title = {A review of 0.18-μm full adder performances for tree structured arithmetic circuits.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#ChangGZ05}, volume = 13, year = 2005 }