%0 Journal Article %1 journals/todaes/LinLHT12 %A Lin, Kuan-Yu %A Lin, Hong-Ting %A Ho, Tsung-Yi %A Tsai, Chia-Chun %D 2012 %J ACM Trans. Design Autom. Electr. Syst. %K dblp %N 3 %P 34:1-34:22 %T Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. %U http://dblp.uni-trier.de/db/journals/todaes/todaes17.html#LinLHT12 %V 17

@article{journals/todaes/LinLHT12, added-at = {2019-09-25T00:00:00.000+0200}, author = {Lin, Kuan-Yu and Lin, Hong-Ting and Ho, Tsung-Yi and Tsai, Chia-Chun}, biburl = {https://www.bibsonomy.org/bibtex/241866900c53da98d230fafeec6b6a0b6/dblp}, ee = {https://doi.org/10.1145/2209291.2209307}, interhash = {1f0d9cba84c1a48c2d55a719edc2ab79}, intrahash = {41866900c53da98d230fafeec6b6a0b6}, journal = {ACM Trans. Design Autom. Electr. Syst.}, keywords = {dblp}, number = 3, pages = {34:1-34:22}, timestamp = {2019-09-26T12:07:32.000+0200}, title = {Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs.}, url = {http://dblp.uni-trier.de/db/journals/todaes/todaes17.html#LinLHT12}, volume = 17, year = 2012 }