%0 Conference Paper %1 conf/dsd/ChenVPS11 %A Chen, Jiaoyan %A Vasudevan, Dilip P. %A Popovici, Emanuel M. %A Schellekens, Michel P. %B DSD %D 2011 %I IEEE Computer Society %K dblp %P 301-308 %T Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. %U http://dblp.uni-trier.de/db/conf/dsd/dsd2011.html#ChenVPS11 %@ 978-1-4577-1048-3

@inproceedings{conf/dsd/ChenVPS11, added-at = {2024-06-04T00:00:00.000+0200}, author = {Chen, Jiaoyan and Vasudevan, Dilip P. and Popovici, Emanuel M. and Schellekens, Michel P.}, biburl = {https://www.bibsonomy.org/bibtex/275116247c23a660bea3199b93f4a0b8f/dblp}, booktitle = {DSD}, crossref = {conf/dsd/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/DSD.2011.44}, interhash = {219f960cfef3411de19b59a76d53d29e}, intrahash = {75116247c23a660bea3199b93f4a0b8f}, isbn = {978-1-4577-1048-3}, keywords = {dblp}, pages = {301-308}, publisher = {IEEE Computer Society}, timestamp = {2024-06-10T07:20:53.000+0200}, title = {Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.}, url = {http://dblp.uni-trier.de/db/conf/dsd/dsd2011.html#ChenVPS11}, year = 2011 }