%0 Conference Paper %1 conf/dsn/MeixnerS06 %A Meixner, Albert %A Sorin, Daniel J. %B DSN %D 2006 %I IEEE Computer Society %K dblp %P 73-82 %T Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. %U http://dblp.uni-trier.de/db/conf/dsn/dsn2006.html#MeixnerS06 %@ 0-7695-2607-1

@inproceedings{conf/dsn/MeixnerS06, added-at = {2023-03-24T00:00:00.000+0100}, author = {Meixner, Albert and Sorin, Daniel J.}, biburl = {https://www.bibsonomy.org/bibtex/2b04722d7a9a314d9a98531b5491b939c/dblp}, booktitle = {DSN}, crossref = {conf/dsn/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/DSN.2006.29}, interhash = {2b93d7e351531164bde8c4b8c76af427}, intrahash = {b04722d7a9a314d9a98531b5491b939c}, isbn = {0-7695-2607-1}, keywords = {dblp}, pages = {73-82}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T16:05:43.000+0200}, title = {Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.}, url = {http://dblp.uni-trier.de/db/conf/dsn/dsn2006.html#MeixnerS06}, year = 2006 }