%0 Conference Paper %1 conf/asscc/CochetCLARA17 %A Cochet, Martin %A Clerc, Sylvain %A Lallement, Guenole %A Abouzeid, Fady %A Roche, Philippe %A Autran, Jean-Luc %B A-SSCC %D 2017 %I IEEE %K dblp %P 69-72 %T A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. %U http://dblp.uni-trier.de/db/conf/asscc/asscc2017.html#CochetCLARA17 %@ 978-1-5386-3178-2

@inproceedings{conf/asscc/CochetCLARA17, added-at = {2022-04-09T00:00:00.000+0200}, author = {Cochet, Martin and Clerc, Sylvain and Lallement, Guenole and Abouzeid, Fady and Roche, Philippe and Autran, Jean-Luc}, biburl = {https://www.bibsonomy.org/bibtex/2ee5340766759d03c5d8f852d6e118fb3/dblp}, booktitle = {A-SSCC}, crossref = {conf/asscc/2017}, ee = {https://doi.org/10.1109/ASSCC.2017.8240218}, interhash = {2c503d0ae98bdb05f96b290bed3a3eb2}, intrahash = {ee5340766759d03c5d8f852d6e118fb3}, isbn = {978-1-5386-3178-2}, keywords = {dblp}, pages = {69-72}, publisher = {IEEE}, timestamp = {2024-04-10T21:35:42.000+0200}, title = {A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking.}, url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2017.html#CochetCLARA17}, year = 2017 }