%0 Conference Paper %1 conf/icassp/MenezABC92 %A Menez, G. %A Auguin, Michel %A Boéri, Fernand %A Carrière, C. %B ICASSP %D 1992 %I IEEE Computer Society %K dblp %P 541-544 %T Automatic generation of architectural models for designing dedicated VLIW signal processors. %U http://dblp.uni-trier.de/db/conf/icassp/icassp1992.html#MenezABC92 %@ 0-7803-0532-9

@inproceedings{conf/icassp/MenezABC92, added-at = {2020-06-29T00:00:00.000+0200}, author = {Menez, G. and Auguin, Michel and Boéri, Fernand and Carrière, C.}, biburl = {https://www.bibsonomy.org/bibtex/2ac5b2e3de86b7234d1a6c6845a5c1b05/dblp}, booktitle = {ICASSP}, crossref = {conf/icassp/1992}, ee = {https://doi.org/10.1109/ICASSP.1992.226563}, interhash = {3a94ebffb203d54a0ea2495079006221}, intrahash = {ac5b2e3de86b7234d1a6c6845a5c1b05}, isbn = {0-7803-0532-9}, keywords = {dblp}, pages = {541-544}, publisher = {IEEE Computer Society}, timestamp = {2024-04-09T13:57:15.000+0200}, title = {Automatic generation of architectural models for designing dedicated VLIW signal processors.}, url = {http://dblp.uni-trier.de/db/conf/icassp/icassp1992.html#MenezABC92}, year = 1992 }