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%0 Conference Paper
%1 conf/iscas/KimKKKKKLLPSS18
%A Kim, Min-Su
%A Kim, Ah-Reum
%A geol Kim, Yong
%A Kim, Chunghee
%A Kim, Dong-Yeop
%A Kim, Jong-Woo
%A Lee, Daeseong
%A Lee, Hyun
%A Pyo, Jungyul
%A Shin, Youngmin
%A Son, Jae Cheol
%B ISCAS
%D 2018
%I IEEE
%K dblp
%P 1-5
%T Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.
%U http://dblp.uni-trier.de/db/conf/iscas/iscas2018.html#KimKKKKKLLPSS18
%@ 978-1-5386-4881-0
@inproceedings{conf/iscas/KimKKKKKLLPSS18,
added-at = {2018-10-24T00:00:00.000+0200},
author = {Kim, Min-Su and Kim, Ah-Reum and geol Kim, Yong and Kim, Chunghee and Kim, Dong-Yeop and Kim, Jong-Woo and Lee, Daeseong and Lee, Hyun and Pyo, Jungyul and Shin, Youngmin and Son, Jae Cheol},
biburl = {https://www.bibsonomy.org/bibtex/2a5eee18c09569f0a1f35fe5236ce1b67/dblp},
booktitle = {ISCAS},
crossref = {conf/iscas/2018},
ee = {https://doi.org/10.1109/ISCAS.2018.8351444},
interhash = {3d29a8312edffd52b5ff3ddb51249a55},
intrahash = {a5eee18c09569f0a1f35fe5236ce1b67},
isbn = {978-1-5386-4881-0},
keywords = {dblp},
pages = {1-5},
publisher = {IEEE},
timestamp = {2018-10-25T11:38:57.000+0200},
title = {Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.},
url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2018.html#KimKKKKKLLPSS18},
year = 2018
}