%0 Journal Article %1 journals/tvlsi/AliotoE14 %A Alioto, Massimo %A Esseni, David %D 2014 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 12 %P 2499-2512 %T Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#AliotoE14 %V 22

@article{journals/tvlsi/AliotoE14, added-at = {2022-10-02T00:00:00.000+0200}, author = {Alioto, Massimo and Esseni, David}, biburl = {https://www.bibsonomy.org/bibtex/299e4729e60ae843048d106b554d1f2ae/dblp}, ee = {https://doi.org/10.1109/TVLSI.2013.2293153}, interhash = {3f8aa6b1acdd036fbc1f0fc7f0b30d7d}, intrahash = {99e4729e60ae843048d106b554d1f2ae}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 12, pages = {2499-2512}, timestamp = {2024-04-08T14:32:59.000+0200}, title = {Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#AliotoE14}, volume = 22, year = 2014 }