%0 Journal Article %1 journals/mj/WangSW17 %A Wang, Deng-Shian %A Su, Yu-Hsun %A Wang, Chua-Chin %D 2017 %J Microelectron. J. %K dblp %P 107-116 %T A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM. %U http://dblp.uni-trier.de/db/journals/mj/mj70.html#WangSW17 %V 70

@article{journals/mj/WangSW17, added-at = {2020-02-22T00:00:00.000+0100}, author = {Wang, Deng-Shian and Su, Yu-Hsun and Wang, Chua-Chin}, biburl = {https://www.bibsonomy.org/bibtex/2f85dbe236244e20ce61982bc828dca19/dblp}, ee = {https://doi.org/10.1016/j.mejo.2017.11.001}, interhash = {3fcd0ebe2498e487861f3594382cfc6a}, intrahash = {f85dbe236244e20ce61982bc828dca19}, journal = {Microelectron. J.}, keywords = {dblp}, pages = {107-116}, timestamp = {2020-02-25T12:59:31.000+0100}, title = {A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM.}, url = {http://dblp.uni-trier.de/db/journals/mj/mj70.html#WangSW17}, volume = 70, year = 2017 }