%0 Journal Article %1 journals/jssc/BergerLS98 %A Berger, Robert %A Lyons, W. Gregory %A Soares, Antonio M. %D 1998 %J IEEE J. Solid State Circuits %K dblp %N 8 %P 1259-1261 %T A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing. %U http://dblp.uni-trier.de/db/journals/jssc/jssc33.html#BergerLS98 %V 33

@article{journals/jssc/BergerLS98, added-at = {2022-07-05T00:00:00.000+0200}, author = {Berger, Robert and Lyons, W. Gregory and Soares, Antonio M.}, biburl = {https://www.bibsonomy.org/bibtex/22e015ea715a15a5d20972f5e7f112228/dblp}, ee = {https://doi.org/10.1109/4.705366}, interhash = {41a3b013a06c46578f019923bf547850}, intrahash = {2e015ea715a15a5d20972f5e7f112228}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 8, pages = {1259-1261}, timestamp = {2024-04-08T10:43:07.000+0200}, title = {A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc33.html#BergerLS98}, volume = 33, year = 1998 }