%0 Conference Paper %1 conf/asicon/DangWLJZ15 %A Dang, Fangyuan %A Wang, Yuan %A Liu, Yuequan %A Jia, Song %A Zhang, Xing %B ASICON %D 2015 %I IEEE %K dblp %P 1-4 %T Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2015.html#DangWLJZ15 %@ 978-1-4799-8485-5

@inproceedings{conf/asicon/DangWLJZ15, added-at = {2018-11-02T00:00:00.000+0100}, author = {Dang, Fangyuan and Wang, Yuan and Liu, Yuequan and Jia, Song and Zhang, Xing}, biburl = {https://www.bibsonomy.org/bibtex/28b95866fbad428b9d062a911febfd45b/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2015}, ee = {https://doi.org/10.1109/ASICON.2015.7517075}, interhash = {444e8bbb086f43b859081cf854f0c028}, intrahash = {8b95866fbad428b9d062a911febfd45b}, isbn = {978-1-4799-8485-5}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2018-11-03T17:08:59.000+0100}, title = {Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2015.html#DangWLJZ15}, year = 2015 }