%0 Journal Article %1 journals/integration/RaviKumarS89 %A Ravikumar, C. P. %A Sastry, Sarma %D 1989 %J Integr. %K dblp %N 3 %P 283-302 %T A hardware accelerator for hierarchical VLSI routing. %U http://dblp.uni-trier.de/db/journals/integration/integration7.html#RaviKumarS89 %V 7

@article{journals/integration/RaviKumarS89, added-at = {2020-02-20T00:00:00.000+0100}, author = {Ravikumar, C. P. and Sastry, Sarma}, biburl = {https://www.bibsonomy.org/bibtex/2954c45ff2508c7ae22177d759b22f6c4/dblp}, ee = {https://doi.org/10.1016/0167-9260(89)90006-0}, interhash = {48b913ef1bf5111b41ec34be8a145780}, intrahash = {954c45ff2508c7ae22177d759b22f6c4}, journal = {Integr.}, keywords = {dblp}, number = 3, pages = {283-302}, timestamp = {2020-02-21T11:53:22.000+0100}, title = {A hardware accelerator for hierarchical VLSI routing.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration7.html#RaviKumarS89}, volume = 7, year = 1989 }