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%0 Thesis
%1 phd/basesearch/Lu06
%A Lu, Xiang
%D 2005
%K
%T Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits.
@phdthesis{phd/basesearch/Lu06,
added-at = {2023-12-12T22:17:58.000+0100},
author = {Lu, Xiang},
biburl = {https://www.bibsonomy.org/bibtex/22ac18ac19dbd09b8c917ddb3f3413508/admin},
ee = {https://www.base-search.net/Record/6e715a67ca9569260ed5c1a2b38e391efa2f37bb240ba647d30e8db9a8aa951c},
interhash = {48f298557e859e7eeec69975730015c3},
intrahash = {2ac18ac19dbd09b8c917ddb3f3413508},
keywords = {},
note = {base-search.net (fttexasamuniv:oai:oaktrust.library.tamu.edu:1969.1/3234)},
school = {Texas A&M University, College Station, USA},
timestamp = {2023-12-12T22:17:58.000+0100},
title = {Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits.},
year = 2005
}