%0 Journal Article %1 journals/tvlsi/SuTWHCWLK08 %A Su, Chin-Lung %A Tsai, Chih-Wea %A Wu, Cheng-Wen %A Hung, Chien-Chung %A Chen, Young-Shying %A Wang, Ding-Yeong %A Lee, Yuan-Jen %A Kao, Ming-Jer %D 2008 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 277-288 %T Write Disturbance Modeling and Testing for MRAM. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#SuTWHCWLK08 %V 16

@article{journals/tvlsi/SuTWHCWLK08, added-at = {2023-09-30T00:00:00.000+0200}, author = {Su, Chin-Lung and Tsai, Chih-Wea and Wu, Cheng-Wen and Hung, Chien-Chung and Chen, Young-Shying and Wang, Ding-Yeong and Lee, Yuan-Jen and Kao, Ming-Jer}, biburl = {https://www.bibsonomy.org/bibtex/208a41d7de550424f189ce0b9d241d70a/dblp}, ee = {https://doi.org/10.1109/TVLSI.2007.915402}, interhash = {4ac561965fb50da58f57ca66c5795d9a}, intrahash = {08a41d7de550424f189ce0b9d241d70a}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {277-288}, timestamp = {2024-04-08T14:32:48.000+0200}, title = {Write Disturbance Modeling and Testing for MRAM.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#SuTWHCWLK08}, volume = 16, year = 2008 }