%0 Journal Article %1 journals/jssc/NakamuraTTNOUSI97 %A Nakamura, Kazuyuki %A Takeda, Koichi %A Toyoshima, Hideo %A Noda, Kenji %A Ohkubo, Hiroaki %A Uchida, Tetsuya %A Shimizu, Toshiyuki %A Itani, Toshiro %A Tokashiki, Ken %A Kishimoto, Koji %D 1997 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1758-1765 %T A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. %U http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#NakamuraTTNOUSI97 %V 32

@article{journals/jssc/NakamuraTTNOUSI97, added-at = {2022-07-21T00:00:00.000+0200}, author = {Nakamura, Kazuyuki and Takeda, Koichi and Toyoshima, Hideo and Noda, Kenji and Ohkubo, Hiroaki and Uchida, Tetsuya and Shimizu, Toshiyuki and Itani, Toshiro and Tokashiki, Ken and Kishimoto, Koji}, biburl = {https://www.bibsonomy.org/bibtex/2ac73b8c7d35e7cf421a9c948f29e0eb1/dblp}, ee = {https://doi.org/10.1109/4.641698}, interhash = {4c5077f3e22e5e7013350aff347ae842}, intrahash = {ac73b8c7d35e7cf421a9c948f29e0eb1}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1758-1765}, timestamp = {2024-04-08T10:44:19.000+0200}, title = {A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#NakamuraTTNOUSI97}, volume = 32, year = 1997 }