%0 Journal Article %1 journals/ieicet/KatohNI09 %A Katoh, Kentaroh %A Namba, Kazuteru %A Ito, Hideo %D 2009 %J IEICE Trans. Inf. Syst. %K dblp %N 2 %P 336-341 %T Design for Delay Fault Testability of 2-Rail Logic Circuits. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet92d.html#KatohNI09 %V 92-D

@article{journals/ieicet/KatohNI09, added-at = {2020-04-11T00:00:00.000+0200}, author = {Katoh, Kentaroh and Namba, Kazuteru and Ito, Hideo}, biburl = {https://www.bibsonomy.org/bibtex/2e54afc7324bdd00aed06a8900792300b/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e92-d_2_336&category=D&year=2009&lang=E&abst=}, interhash = {507dbc219e4158f73cc0dd58420f816e}, intrahash = {e54afc7324bdd00aed06a8900792300b}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 2, pages = {336-341}, timestamp = {2020-04-14T11:48:57.000+0200}, title = {Design for Delay Fault Testability of 2-Rail Logic Circuits.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet92d.html#KatohNI09}, volume = {92-D}, year = 2009 }