%0 Journal Article %1 journals/vlsisp/RamanathanNV00 %A Ramanathan, S. %A Nandy, S. K. %A Visvanathan, V. %D 2000 %J J. VLSI Signal Process. %K dblp %N 3 %P 333-359 %T Reconfigurable Filter Coprocessor Architecture for DSP Applications. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp26.html#RamanathanNV00 %V 26

@article{journals/vlsisp/RamanathanNV00, added-at = {2021-04-27T00:00:00.000+0200}, author = {Ramanathan, S. and Nandy, S. K. and Visvanathan, V.}, biburl = {https://www.bibsonomy.org/bibtex/2802de9c62cce97b7e5258a6fe529c9a8/dblp}, ee = {https://doi.org/10.1023/A:1026555400883}, interhash = {51bf0ac158e7efaf99d0d21b798a0692}, intrahash = {802de9c62cce97b7e5258a6fe529c9a8}, journal = {J. VLSI Signal Process.}, keywords = {dblp}, number = 3, pages = {333-359}, timestamp = {2024-04-09T03:12:00.000+0200}, title = {Reconfigurable Filter Coprocessor Architecture for DSP Applications.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp26.html#RamanathanNV00}, volume = 26, year = 2000 }