%0 Journal Article %1 journals/jssc/ChangRSTHHCTKLD05 %A Chang, Jonathan %A Rusu, Stefan %A Shoemaker, Jonathan %A Tam, Simon %A Huang, Ming %A Haque, Mizan %A Chiu, Siufu %A Truong, Kevin %A Karim, Mesbah %A Leong, Gloria %A Desai, Kiran %A Goe, Richard %A Kulkarni, Sandhya %D 2005 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 195-203 %T A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#ChangRSTHHCTKLD05 %V 40

@article{journals/jssc/ChangRSTHHCTKLD05, added-at = {2022-03-14T00:00:00.000+0100}, author = {Chang, Jonathan and Rusu, Stefan and Shoemaker, Jonathan and Tam, Simon and Huang, Ming and Haque, Mizan and Chiu, Siufu and Truong, Kevin and Karim, Mesbah and Leong, Gloria and Desai, Kiran and Goe, Richard and Kulkarni, Sandhya}, biburl = {https://www.bibsonomy.org/bibtex/2db4eb4fcae0d31fd57cce34e5fe27ca2/dblp}, ee = {https://doi.org/10.1109/JSSC.2004.837970}, interhash = {574993f71bdb007b9ca87cc742b3fda3}, intrahash = {db4eb4fcae0d31fd57cce34e5fe27ca2}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {195-203}, timestamp = {2024-04-08T10:43:23.000+0200}, title = {A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#ChangRSTHHCTKLD05}, volume = 40, year = 2005 }