%0 Conference Paper %1 conf/ipps/GatesKLPD17 %A Gates, Mark %A Kurzak, Jakub %A Luszczek, Piotr %A Pei, Yu %A Dongarra, Jack J. %B IPDPS Workshops %D 2017 %I IEEE Computer Society %K dblp %P 1408-1417 %T Autotuning Batch Cholesky Factorization in CUDA with Interleaved Layout of Matrices. %U http://dblp.uni-trier.de/db/conf/ipps/ipdps2017w.html#GatesKLPD17 %@ 978-1-5386-3408-0

@inproceedings{conf/ipps/GatesKLPD17, added-at = {2023-03-24T00:00:00.000+0100}, author = {Gates, Mark and Kurzak, Jakub and Luszczek, Piotr and Pei, Yu and Dongarra, Jack J.}, biburl = {https://www.bibsonomy.org/bibtex/221a1cf5583c74ae49f226205dacfa7f8/dblp}, booktitle = {IPDPS Workshops}, crossref = {conf/ipps/2017w}, ee = {https://doi.ieeecomputersociety.org/10.1109/IPDPSW.2017.18}, interhash = {576807a519a28c7b8d41ed058c39e859}, intrahash = {21a1cf5583c74ae49f226205dacfa7f8}, isbn = {978-1-5386-3408-0}, keywords = {dblp}, pages = {1408-1417}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T13:27:58.000+0200}, title = {Autotuning Batch Cholesky Factorization in CUDA with Interleaved Layout of Matrices.}, url = {http://dblp.uni-trier.de/db/conf/ipps/ipdps2017w.html#GatesKLPD17}, year = 2017 }