%0 Journal Article %1 journals/vlsisp/PedramV97 %A Pedram, Massoud %A Vaishnav, Hirendu %D 1997 %J VLSI Signal Processing %K dblp %N 3 %P 221-232 %T Power Optimization in VLSI Layout: A Survey. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp15.html#PedramV97 %V 15

@article{journals/vlsisp/PedramV97, added-at = {2008-08-07T00:00:00.000+0200}, author = {Pedram, Massoud and Vaishnav, Hirendu}, biburl = {https://www.bibsonomy.org/bibtex/2f8097cdc1b7e6851b9949d71cd765461/dblp}, date = {2008-08-07}, description = {dblp}, ee = {http://dx.doi.org/10.1023/A:1007907110303}, interhash = {5e2cdd70cb3783c0738c42a11af9243d}, intrahash = {f8097cdc1b7e6851b9949d71cd765461}, journal = {VLSI Signal Processing}, keywords = {dblp}, number = 3, pages = {221-232}, timestamp = {2008-08-08T11:54:23.000+0200}, title = {Power Optimization in VLSI Layout: A Survey.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp15.html#PedramV97}, volume = 15, year = 1997 }