%0 Journal Article %1 journals/jssc/HashimotoKHKTSN18 %A Hashimoto, Tetsutaro %A Kawabe, Yukihito %A Hara, Michiharu %A Kakimura, Yasushi %A Tajiri, Kunihiko %A Shirota, Shinichiro %A Nishiyama, Ryuichi %A Sakurai, Hitoshi %A Okano, Hiroshi %A Tomita, Yasumoto %A Satoh, Sugio %A Yamashita, Hideo %D 2018 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 1028-1037 %T An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. %U http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#HashimotoKHKTSN18 %V 53

@article{journals/jssc/HashimotoKHKTSN18, added-at = {2020-08-30T00:00:00.000+0200}, author = {Hashimoto, Tetsutaro and Kawabe, Yukihito and Hara, Michiharu and Kakimura, Yasushi and Tajiri, Kunihiko and Shirota, Shinichiro and Nishiyama, Ryuichi and Sakurai, Hitoshi and Okano, Hiroshi and Tomita, Yasumoto and Satoh, Sugio and Yamashita, Hideo}, biburl = {https://www.bibsonomy.org/bibtex/24c6a96ac6daba9043c453378e3f85c65/dblp}, ee = {https://doi.org/10.1109/JSSC.2017.2777101}, interhash = {6cf99394a4c306d921bd28d662e100cd}, intrahash = {4c6a96ac6daba9043c453378e3f85c65}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {1028-1037}, timestamp = {2020-08-31T11:41:04.000+0200}, title = {An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#HashimotoKHKTSN18}, volume = 53, year = 2018 }