32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.
Please log in to take part in the discussion (add own reviews or comments).
Cite this publication
More citation styles
- please select -
%0 Conference Paper
%1 conf/isscc/WuYGCLCSC21
%A Wu, Wanghua
%A Yao, Chih-Wei
%A Guo, Chengkai
%A Chiang, Pei-Yuan
%A Lau, Pak-Kim
%A Chen, Lei
%A Son, Sang Won
%A Cho, Thomas Byunghak
%B ISSCC
%D 2021
%I IEEE
%K dblp
%P 444-446
%T 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2021.html#WuYGCLCSC21
%@ 978-1-7281-9549-0
@inproceedings{conf/isscc/WuYGCLCSC21,
added-at = {2021-03-10T00:00:00.000+0100},
author = {Wu, Wanghua and Yao, Chih-Wei and Guo, Chengkai and Chiang, Pei-Yuan and Lau, Pak-Kim and Chen, Lei and Son, Sang Won and Cho, Thomas Byunghak},
biburl = {https://www.bibsonomy.org/bibtex/21e54b89335abc7f20d813710f1b30228/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2021},
ee = {https://doi.org/10.1109/ISSCC42613.2021.9365850},
interhash = {6e34410a5e2d12d42bef2bec3bcd8920},
intrahash = {1e54b89335abc7f20d813710f1b30228},
isbn = {978-1-7281-9549-0},
keywords = {dblp},
pages = {444-446},
publisher = {IEEE},
timestamp = {2024-04-09T20:43:12.000+0200},
title = {32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2021.html#WuYGCLCSC21},
year = 2021
}
