%0 Conference Paper %1 conf/aspdac/KaneckoT97 %A Kanecko, M. %A Tian, Jialin %B ASP-DAC %D 1997 %I IEEE %K dblp %P 247-252 %T Concurrent cell generation and mapping for CMOS logic circuits. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac1997.html#KaneckoT97 %@ 0-7803-3663-1

@inproceedings{conf/aspdac/KaneckoT97, added-at = {2017-05-26T00:00:00.000+0200}, author = {Kanecko, M. and Tian, Jialin}, biburl = {https://www.bibsonomy.org/bibtex/28257ce70e4ca986f37aa67c2c6a14c59/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/1997}, ee = {https://doi.org/10.1109/ASPDAC.1997.600134}, interhash = {6e57ca73faa460b117f28ac860da393f}, intrahash = {8257ce70e4ca986f37aa67c2c6a14c59}, isbn = {0-7803-3663-1}, keywords = {dblp}, pages = {247-252}, publisher = {IEEE}, timestamp = {2019-10-17T16:45:14.000+0200}, title = {Concurrent cell generation and mapping for CMOS logic circuits.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac1997.html#KaneckoT97}, year = 1997 }