%0 Journal Article %1 journals/tvlsi/SungCYK14 %A Sung, Hyungsu %A Cho, Keewon %A Yoon, Kunsang %A Kang, Sungho %D 2014 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 11 %P 2380-2387 %T A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#SungCYK14 %V 22

@article{journals/tvlsi/SungCYK14, added-at = {2024-07-15T00:00:00.000+0200}, author = {Sung, Hyungsu and Cho, Keewon and Yoon, Kunsang and Kang, Sungho}, biburl = {https://www.bibsonomy.org/bibtex/275ba1adfded6daf581aea5f6e9fcb845/dblp}, ee = {https://doi.org/10.1109/TVLSI.2013.2289964}, interhash = {6e8184d564af6f8e5ec0b6cc4eb3542c}, intrahash = {75ba1adfded6daf581aea5f6e9fcb845}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 11, pages = {2380-2387}, timestamp = {2024-07-22T07:05:10.000+0200}, title = {A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#SungCYK14}, volume = 22, year = 2014 }