%0 Conference Paper %1 conf/iscas/GrycelW20 %A Grycel, Jacob T. %A Walls, Robert J. %B ISCAS %D 2020 %I IEEE %K dblp %P 1-5 %T DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2020.html#GrycelW20 %@ 978-1-7281-3320-1

@inproceedings{conf/iscas/GrycelW20, added-at = {2021-01-18T00:00:00.000+0100}, author = {Grycel, Jacob T. and Walls, Robert J.}, biburl = {https://www.bibsonomy.org/bibtex/275c842a46f62ac2f3ea24802e80e2aed/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2020}, ee = {https://doi.org/10.1109/ISCAS45731.2020.9181186}, interhash = {70f560831113e980ac6ec7ff5139d3e0}, intrahash = {75c842a46f62ac2f3ea24802e80e2aed}, isbn = {978-1-7281-3320-1}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2024-04-09T21:27:50.000+0200}, title = {DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2020.html#GrycelW20}, year = 2020 }