%0 Conference Paper %1 conf/asscc/MaSLR17 %A Ma, Shunli %A Sheng, Jili %A Li, Ning %A Ren, Junyan %B A-SSCC %D 2017 %I IEEE %K dblp %P 321-324 %T A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/asscc/asscc2017.html#MaSLR17 %@ 978-1-5386-3178-2

@inproceedings{conf/asscc/MaSLR17, added-at = {2018-06-09T00:00:00.000+0200}, author = {Ma, Shunli and Sheng, Jili and Li, Ning and Ren, Junyan}, biburl = {https://www.bibsonomy.org/bibtex/24045faa8d3558446025e0adf3aecc03b/dblp}, booktitle = {A-SSCC}, crossref = {conf/asscc/2017}, ee = {https://doi.org/10.1109/ASSCC.2017.8240281}, interhash = {73253390eb928adfcc8df7143a3069a6}, intrahash = {4045faa8d3558446025e0adf3aecc03b}, isbn = {978-1-5386-3178-2}, keywords = {dblp}, pages = {321-324}, publisher = {IEEE}, timestamp = {2018-06-12T11:43:21.000+0200}, title = {A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2017.html#MaSLR17}, year = 2017 }