%0 Journal Article %1 journals/anor/AndreattaR94 %A Andreatta, Alexandre A. %A Ribeiro, Celso C. %D 1994 %J Ann. Oper. Res. %K dblp %N 1 %P 1-36 %T A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits. %U http://dblp.uni-trier.de/db/journals/anor/anor50.html#AndreattaR94 %V 50

@article{journals/anor/AndreattaR94, added-at = {2022-04-09T00:00:00.000+0200}, author = {Andreatta, Alexandre A. and Ribeiro, Celso C.}, biburl = {https://www.bibsonomy.org/bibtex/257b79fdc35c3d18713810d3551d9876d/dblp}, ee = {https://doi.org/10.1007/BF02085633}, interhash = {78c5b46d1bd04f3af22de560e92647ee}, intrahash = {57b79fdc35c3d18713810d3551d9876d}, journal = {Ann. Oper. Res.}, keywords = {dblp}, number = 1, pages = {1-36}, timestamp = {2024-04-08T10:58:28.000+0200}, title = {A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits.}, url = {http://dblp.uni-trier.de/db/journals/anor/anor50.html#AndreattaR94}, volume = 50, year = 1994 }