%0 Journal Article %1 journals/ieicet/OhS16 %A Oh, Sangheon %A Shin, Changhwan %D 2016 %J IEICE Trans. Electron. %K dblp %N 5 %P 541-543 %T Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet99c.html#OhS16 %V 99-C

@article{journals/ieicet/OhS16, added-at = {2020-04-11T00:00:00.000+0200}, author = {Oh, Sangheon and Shin, Changhwan}, biburl = {https://www.bibsonomy.org/bibtex/22c7ec47b7228b5dfd7f03adc2b351f39/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e99-c_5_541}, interhash = {7d0b35fcf888b1014c49d9d5238376ac}, intrahash = {2c7ec47b7228b5dfd7f03adc2b351f39}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 5, pages = {541-543}, timestamp = {2020-04-14T11:48:40.000+0200}, title = {Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet99c.html#OhS16}, volume = {99-C}, year = 2016 }