%0 Journal Article %1 journals/tvlsi/KimKMR05 %A Kim, Chris H. %A Kim, Jae-Joon %A Mukhopadhyay, Saibal %A Roy, Kaushik %D 2005 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 349-357 %T A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#KimKMR05 %V 13

@article{journals/tvlsi/KimKMR05, added-at = {2020-03-11T00:00:00.000+0100}, author = {Kim, Chris H. and Kim, Jae-Joon and Mukhopadhyay, Saibal and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/254d14d0711b50802d42b17510ecd8b5b/dblp}, ee = {https://doi.org/10.1109/TVLSI.2004.842903}, interhash = {7dfebb6374645c9c9a6599e55dc46572}, intrahash = {54d14d0711b50802d42b17510ecd8b5b}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {349-357}, timestamp = {2020-03-12T11:41:50.000+0100}, title = {A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#KimKMR05}, volume = 13, year = 2005 }