%0 Conference Paper %1 conf/isscc/TamLLCVA06 %A Tam, Simon %A Leung, Justin %A Limaye, Rahul Dilip %A Choy, Sam %A Vora, Sujal %A Adachi, Mitsuhiro %B ISSCC %D 2006 %I IEEE %K dblp %P 1512-1521 %T Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2006.html#TamLLCVA06 %@ 1-4244-0079-1

@inproceedings{conf/isscc/TamLLCVA06, added-at = {2021-01-15T00:00:00.000+0100}, author = {Tam, Simon and Leung, Justin and Limaye, Rahul Dilip and Choy, Sam and Vora, Sujal and Adachi, Mitsuhiro}, biburl = {https://www.bibsonomy.org/bibtex/223f00bd5a8c3e4f798e73e84631054f8/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2006}, ee = {https://doi.org/10.1109/ISSCC.2006.1696202}, interhash = {7efede380f57c26f2ed0b62b14c262a7}, intrahash = {23f00bd5a8c3e4f798e73e84631054f8}, isbn = {1-4244-0079-1}, keywords = {dblp}, pages = {1512-1521}, publisher = {IEEE}, timestamp = {2024-04-09T20:43:22.000+0200}, title = {Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2006.html#TamLLCVA06}, year = 2006 }