%0 Journal Article %1 journals/jssc/ZhaoBDKLNNSV99 %A Zhao, Cangsang %A Bhattacharya, Uddalak %A Denham, Martin %A Kolousek, Jim %A Lu, Yi %A Ng, Yong-Gee %A Nintunze, Novat %A Sarkez, Kamal %A Varadarajan, Hemmige D. %D 1999 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1564-1570 %T An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. %U http://dblp.uni-trier.de/db/journals/jssc/jssc34.html#ZhaoBDKLNNSV99 %V 34

@article{journals/jssc/ZhaoBDKLNNSV99, added-at = {2022-07-05T00:00:00.000+0200}, author = {Zhao, Cangsang and Bhattacharya, Uddalak and Denham, Martin and Kolousek, Jim and Lu, Yi and Ng, Yong-Gee and Nintunze, Novat and Sarkez, Kamal and Varadarajan, Hemmige D.}, biburl = {https://www.bibsonomy.org/bibtex/2400dfc824fb64671a228deddd1f8571a/dblp}, ee = {https://doi.org/10.1109/4.799864}, interhash = {80690d1f0cdae049235c16e36e958ac2}, intrahash = {400dfc824fb64671a228deddd1f8571a}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1564-1570}, timestamp = {2024-04-08T10:44:14.000+0200}, title = {An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc34.html#ZhaoBDKLNNSV99}, volume = 34, year = 1999 }