%0 Conference Paper %1 conf/sies/TrillaHAC17 %A Trilla, David %A Hernández, Carles %A Abella, Jaume %A Cazorla, Francisco J. %B SIES %D 2017 %I IEEE %K dblp %P 1-8 %T Modelling bus contention during system early design stages. %U http://dblp.uni-trier.de/db/conf/sies/sies2017.html#TrillaHAC17 %@ 978-1-5386-3166-9

@inproceedings{conf/sies/TrillaHAC17, added-at = {2023-07-14T00:00:00.000+0200}, author = {Trilla, David and Hernández, Carles and Abella, Jaume and Cazorla, Francisco J.}, biburl = {https://www.bibsonomy.org/bibtex/22beb229f51ce3738f80b2c2318a7c0c4/dblp}, booktitle = {SIES}, crossref = {conf/sies/2017}, ee = {https://doi.org/10.1109/SIES.2017.7993393}, interhash = {853e469dad2b5de19ced83b52c6dedd8}, intrahash = {2beb229f51ce3738f80b2c2318a7c0c4}, isbn = {978-1-5386-3166-9}, keywords = {dblp}, pages = {1-8}, publisher = {IEEE}, timestamp = {2024-04-10T08:30:14.000+0200}, title = {Modelling bus contention during system early design stages.}, url = {http://dblp.uni-trier.de/db/conf/sies/sies2017.html#TrillaHAC17}, year = 2017 }