%0 Journal Article %1 journals/jssc/UytterhoevenD22 %A Uytterhoeven, Roel %A Dehaene, Wim %D 2022 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 651-660 %T Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#UytterhoevenD22 %V 57

@article{journals/jssc/UytterhoevenD22, added-at = {2022-02-08T00:00:00.000+0100}, author = {Uytterhoeven, Roel and Dehaene, Wim}, biburl = {https://www.bibsonomy.org/bibtex/207248edbe5de5b9854b5ad351b3b1ea3/dblp}, ee = {https://doi.org/10.1109/JSSC.2021.3106245}, interhash = {8b30c9e898db410b34d59da13c2b5738}, intrahash = {07248edbe5de5b9854b5ad351b3b1ea3}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 2, pages = {651-660}, timestamp = {2024-04-08T10:43:19.000+0200}, title = {Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#UytterhoevenD22}, volume = 57, year = 2022 }