%0 Conference Paper %1 conf/fpl/MatasaruJ00 %A Matasaru, Bogdan %A Jebelean, Tudor %B FPL %D 2000 %E Hartenstein, Reiner W. %E Grünbacher, Herbert %I Springer %K dblp %P 810-813 %T FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2000.html#MatasaruJ00 %V 1896 %@ 3-540-67899-9

@inproceedings{conf/fpl/MatasaruJ00, added-at = {2017-05-21T00:00:00.000+0200}, author = {Matasaru, Bogdan and Jebelean, Tudor}, biburl = {https://www.bibsonomy.org/bibtex/2ecd851638ec78590354e248efb4e897b/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2000}, editor = {Hartenstein, Reiner W. and Grünbacher, Herbert}, ee = {https://doi.org/10.1007/3-540-44614-1_91}, interhash = {8c414c1bf743df2fd754c3b9ca82c4ec}, intrahash = {ecd851638ec78590354e248efb4e897b}, isbn = {3-540-67899-9}, keywords = {dblp}, pages = {810-813}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-05-15T17:15:03.000+0200}, title = {FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2000.html#MatasaruJ00}, volume = 1896, year = 2000 }