%0 Journal Article %1 journals/vlsisp/OsorioV03 %A Osorio, Roberto R. %A Vanhoof, Bart %D 2003 %J VLSI Signal Processing %K dblp %N 3 %P 267-275 %T High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp33.html#OsorioV03 %V 33

@article{journals/vlsisp/OsorioV03, added-at = {2008-07-22T00:00:00.000+0200}, author = {Osorio, Roberto R. and Vanhoof, Bart}, biburl = {https://www.bibsonomy.org/bibtex/2d5de1a6d98938987942cb711bafe9192/dblp}, date = {2008-07-22}, description = {dblp}, ee = {http://dx.doi.org/10.1023/A:1022123829466}, interhash = {8cc5f991e5f454dab3d852904f510557}, intrahash = {d5de1a6d98938987942cb711bafe9192}, journal = {VLSI Signal Processing}, keywords = {dblp}, number = 3, pages = {267-275}, timestamp = {2008-07-23T11:59:52.000+0200}, title = {High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp33.html#OsorioV03}, volume = 33, year = 2003 }