%0 Conference Paper %1 conf/isca/HrishikeshBKSJF02 %A Hrishikesh, M. S. %A Burger, Doug %A Keckler, Stephen W. %A Shivakumar, Premkishore %A Jouppi, Norman P. %A Farkas, Keith I. %B ISCA %D 2002 %E Patt, Yale N. %E Grunwald, Dirk %E Skadron, Kevin %I IEEE Computer Society %K dblp %P 14-24 %T The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. %U http://dblp.uni-trier.de/db/conf/isca/isca2002.html#HrishikeshBKSJF02 %@ 0-7695-1605-X

@inproceedings{conf/isca/HrishikeshBKSJF02, added-at = {2023-03-24T00:00:00.000+0100}, author = {Hrishikesh, M. S. and Burger, Doug and Keckler, Stephen W. and Shivakumar, Premkishore and Jouppi, Norman P. and Farkas, Keith I.}, biburl = {https://www.bibsonomy.org/bibtex/2cf23d00717637c6f11dc0b1b75c4c8fb/dblp}, booktitle = {ISCA}, crossref = {conf/isca/2002}, editor = {Patt, Yale N. and Grunwald, Dirk and Skadron, Kevin}, ee = {http://dl.acm.org/citation.cfm?id=545218}, interhash = {9492be41cfacb5e29cfdfa86878e31c8}, intrahash = {cf23d00717637c6f11dc0b1b75c4c8fb}, isbn = {0-7695-1605-X}, keywords = {dblp}, pages = {14-24}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T09:12:06.000+0200}, title = {The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.}, url = {http://dblp.uni-trier.de/db/conf/isca/isca2002.html#HrishikeshBKSJF02}, year = 2002 }