%0 Conference Paper %1 conf/fpl/PearsonMPNGGM05 %A Pearson, Martin J. %A Melhuish, Chris %A Pipe, Anthony G. %A Nibouche, Mokhtar %A Gilhespy, Ian %A Gurney, Kevin N. %A Mitchinson, Benjamin %B FPL %D 2005 %E Rissa, Tero %E Wilton, Steven J. E. %E Leong, Philip Heng Wai %I IEEE %K dblp %P 582-585 %T Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#PearsonMPNGGM05 %@ 0-7803-9362-7

@inproceedings{conf/fpl/PearsonMPNGGM05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Pearson, Martin J. and Melhuish, Chris and Pipe, Anthony G. and Nibouche, Mokhtar and Gilhespy, Ian and Gurney, Kevin N. and Mitchinson, Benjamin}, biburl = {https://www.bibsonomy.org/bibtex/246e16c910206db109829166d592052a3/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2005}, editor = {Rissa, Tero and Wilton, Steven J. E. and Leong, Philip Heng Wai}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515790}, interhash = {9a5814d2313f0b68ba743a23e352e481}, intrahash = {46e16c910206db109829166d592052a3}, isbn = {0-7803-9362-7}, keywords = {dblp}, pages = {582-585}, publisher = {IEEE}, timestamp = {2024-04-10T14:52:35.000+0200}, title = {Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#PearsonMPNGGM05}, year = 2005 }